IEEE Computer Society. Design Automation Standards Committee

• IEEE standard for SystemVerilog--unified hardware design, specification, and verification language
• IEEE standard VHDL mathematical packages
• IEEE standard for VHDL register transfer level (RTL) synthesis
• IEEE standard for VHDL waveform and vector exchange to support design and test verification (WAVES) language reference manual
• IEEE Standard VHDL analog and mixed-signal extensions
• IEEE standard for property specification language (PSL)
• IEEE standard interface for hardware description models of electronic components