Power Aware Memory System Design for Very Deep SubMicron (VDSM) SoCs

Power Aware Memory System Design for Very Deep SubMicron (VDSM) SoCs

123 pages· 2009· ISBN 9781109157673
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Through analysis, we establish that using multi-port memory in L1 cache that supports high Instructions Per Cycle (IPC), and multi-banked, multi-array configurations for large L2 caches, achieves leakage power savings. Our analysis on various memory and architectural solutions in terms of throughput and power consumption based on a set of benchmark applications provides architectural choices for reducing the memory performance gap.

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