Verification by Error Modeling

Verification by Error Modeling

Using Testing Techniques in Hardware Verification

by Zeljko Zilic, Katarzyna Radecka

216 pages· 2006· ISBN 9780306487392
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This book presents the basis for reusing the test vector generation and simulation for the purpose of implementation verification, to result in a significant timesaving. It brings the results in the direction of merging manufacturing test vector generation and verification.

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