Optimization of Column Compression Multipliers

With delay proportional to the logarithm of the multiplier word length, column compression multipliers are the fastest multipliers. Unfortunately, since the design community has assumed that fast multiplication can only be realized through custom design and layout, column compression multipliers are often dismissed as too time consuming and complex because of their irregular structure. This research demonstrates that an automated multiplier generation and layout process makes the column compression multiplier a viable option for application specific CMOS products. Techniques for optimal multiplier designs are identified through analysis of area, delay, and power characteristics of Wallace, Dadda, and Reduced Area multipliers.